A prior art TTL to CMOS translating input buffer circuit consisting of first and second CMOS inverter stages is illustrated in FIG. 1. The first inverter stage P1,N1 is coupled between the input V.sub.IN and an intermediate output node m1. The second inverter stage P2, N2 is coupled between the intermediate node m1 and the output V.sub.OUT. The inverter stages P1,N1 and P2,N2 are coupled between high and low potential power rails V.sub.CCQ and GNDQ. The high potential power rail V.sub.CCQ voltage at, for example 5.0 v, and the low potential power rail GNDQ voltage at, for example 0 v, represent the CMOS logic high and low potential levels.
TTL high and low potential level data signals, typically 2.0-2.4 v high and 0.4-0.8 v low are applied at the input V.sub.IN. The ratio of respective channel widths of the PMOS pullup transistor P1 and NMOS pulldown transistor N1 of the first inverter stage is skewed to provide a TTL switching threshold voltage level at the input V.sub.IN of typically 1.5 v. To achieve this TTL switching threshold voltage, the ratio of channel widths P1/N1 is typically 1/4.
An LH transition to a TTL high potential level data signal H at the input V.sub.IN turns on the NMOS pulldown transistor N1 to cause a low potential data signal L at the intermediate output node m1. The TTL high potential signal H is not sufficient however to complete turn off of PMOS pullup transistor P1 causing an unwanted static current or crowbar current I.sub.CCT to flow through P1 and N1 during a steady state low potential data signal L at the intermediate node m1. Transistor P1 is therefore sized for a small channel width to restrict and limit the undesirable power dissipating static current I.sub.CCT to an acceptable specified level.
Typical values for channel widths of P1/N1 are, for example, 25 .mu./100 .mu. for the same channel length. While this skewed ratio and small size P1 channel width limits static current I.sub.CCT to a specified level, it slows the LH transition from low to high potential level at intermediate output node m1. Data signals reach the CMOS logic power rail voltage levels of 0 v and 5.0 v at the intermediate node m1 but with reduced speed and with unwanted power dissipation.
Intermediate node m1 drives the second CMOS inverter stage P2,N2 which is selected to have channel widths in a standard ratio range of for example 1/1 to 1/2. Example values for channel widths of P2,N2 are, for example 150 .mu./150 .mu. for the same channel length. The second CMOS inverter stage P2,N2 with standard ratio channel widths switches at the CMOS threshold voltage of e.g. 2.5 v and completes the non-skewed translation to CMOS logic high and low potential level data signals at the output V.sub.OUT. Output signals at V.sub.OUT are available to drive other CMOS or BICMOS circuits.